A technology for bonding a semiconductor chip to a substrate is known. Japanese laid-open patent application publication No. 2001-57468 discloses such a soldering technology for bonding a semiconductor chip on a substrate.
In the circuit device disclosed in the above publication, with a thin solder layer, a chip is bonded to a substrate. The device comprises a substrate with a metallization layer on the surface thereof, a chip, and a solder layer for bonding the chip to the metallization layer on the substrate to mount the chip on the substrate.
The solder layer comprises an Au—Sn alloy having a eutectic composition defined by a eutectic point of Au—Sn alloy. The Au—Sn alloy includes Sn of 29 at. % and the balance Au. The eutectic point is 278° C. In this circuit device, there are further provided barrier layers between the solder layer and the metallization layer to prevent a reaction between the solder layer and the Au layer and between the solder layer and a metal layer in the metallization layer, respectively. The barrier layer comprises a δ-phase Au—Sn alloy. In this circuit device, it is difficult to detect timing of mounting a semiconductor chip on the substrate and a mounting position of the semiconductor chip on the melting solder layer on the substrate.